UCIEE

List of executables under Creator/bin directory: cydsfit cydsfit -p <projfile> [-d <device>] [-s <srcpath>] [-f <flowtype>] [option ...] [--] [option ...]     -h                Display this help message.     -p <projfile>     Specify the name of the top level project file.     -d <device>       Override the selected device stored in the project file.     -s <srcpath>      Location of previously generated source. Used when merging                         user editable sections in to the new code. Defaults to                   ...

PSoC Creator automatically generate a verilog file of your schematic design. This verilog file (PROJ_NAME.v) is under codegentemp directory located on your project directory. Here's the verilog from a empty project using the CY8CKIT-059 PSoC 5LP kit: // ====================================================================== // Design01.v generated from TopDesign.cysch // 01/11/2017 at 16:34 // This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!! // ====================================================================== /* -- WARNING: The following section of defines are deprecated and will be removed in a future release -- */ `define CYDEV_CHIP_DIE_LEOPARD 1 `define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3 `define CYDEV_CHIP_REV_LEOPARD_ES3 3 `define CYDEV_CHIP_REV_LEOPARD_ES2 1 `define CYDEV_CHIP_REV_LEOPARD_ES1 0 `define CYDEV_CHIP_DIE_TMA4 2 `define CYDEV_CHIP_REV_TMA4_PRODUCTION 17 `define CYDEV_CHIP_REV_TMA4_ES 17 `define CYDEV_CHIP_REV_TMA...